The invention relates to the field of virtual substrates, and in particular to coplanar integration of lattice-mismatched semiconductors with silicon via wafer bonding virtual substrates.
The large lattice constant mismatch between Si and GaAs/Ge precludes direct growth of the mismatched material directly on Si without nucleation of a high density of defects. One solution to this limitation is growth of compositionally graded layers where a large lattice constant mismatch is spread across several low-mismatch interfaces, thereby minimizing nucleation of threading dislocations. Compositional grading of relaxed Si1-xGex layers of increasing Ge fraction can be used to create an arbitrary lattice constant ranging from that of Si to Ge on a bulk Si substrate. Such a structure is termed a virtual substrate.
Ge virtual substrates could further be used to integrate GaAs with Si since the lattice mismatch between Ge and GaAs is low. Unfortunately, the virtual substrate approach has the disadvantage of requiring a thick graded buffer to ensure complete relaxation of the individual mismatched layers. In the case of Ge virtual substrates, which are graded from Si to pure Ge, the buffer thickness is typically greater than 10 μm. Such thick layers 2 result in severe wafer bow due to thermal stress and complicate integration of the mismatched material with the underlying Si 4 since the device levels are not coplanar and must be interconnected across a deep step, as shown in FIG. 1.
Wafer bonding and layer transfer is another approach for integrating low-defect, lattice mismatched materials, as shown in FIG. 2. In this approach, two flat, clean wafer 6, 8 surfaces are brought into contact and annealed at high temperatures to create a strong bond. A thin layer of material is then transferred from the seed wafer to the handle wafer by means of grind and etch-back with the aid of an etch-stop layer or layer exfoliation by hydrogen ion implantation. However, the differing coefficients of thermal expansion (CTE) of Si relative to GaAs and Ge limit the annealing temperature that these bonded pairs can be exposed to. In addition, wafer size mismatch limits their use to non-leading edge fabrication facilities.